Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers

ABSTRACT

Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias. In a second 3D integration scheme, a blanket silicon-on-insulator (SOI) substrate having a first SOI layer of a first crystallographic orientation is bonded to a surface of a pre-fabricating wafer having second semiconductor devices on a second SOI layer that has a different crystallographic orientation than the first SOI layer; and forming first semiconductor device on the first SOI layer.

FIELD OF THE INVENTION

The present invention relates to complementary metal oxide semiconductor(CMOS) integrated circuits, and more particularly to three-dimensionalCMOS integrated circuits having semiconductor device layers that arebuilt on different crystal oriented wafers.

BACKGROUND OF THE INVENTION

In present semiconductor technology, CMOS devices, such as nFETs orpFETs, are typically fabricated upon semiconductor wafers, such as Si,that have a single crystal orientation. In particular, most of today'ssemiconductor devices are built upon Si having a (100) crystalorientation.

Electrons are known to have a high mobility for a (100) Si surfaceorientation, but holes are known to have high mobility for a (110)surface orientation. That is, hole mobility values on (100) Si areroughly 2×-4× lower than the corresponding electron hole mobility forthis crystallographic orientation. To compensate for this discrepancy,pFETs are typically designed with larger widths in order to balancepull-up currents against the nFET pull-down currents and achieve uniformcircuit switching pFETs having larger widths are undesirable since theytake up a significant amount of chip area.

On the other hand, hole mobilities on (110) Si are 2× higher than on(100) Si; therefore, pFETs formed on a (110) surface will exhibitsignificantly higher drive currents than pFETs formed on a (100)surface. Unfortunately, electron mobilities on (110) Si surfaces aresignificantly degraded compared to (100) Si surfaces.

As can be deduced from the above discussion, the (110) Si surface isoptimal for pFET devices because of excellent hole mobility, yet such acrystal orientation is completely inappropriate for nFET devices.Instead, the (100) Si surface is optimal for nFET devices since thatcrystal orientation favors electron mobility.

It is becoming more difficult to achieve substantial integrated circuit(IC) performance enhancement by traditional CMOS device and interconnectscaling. New materials introduced into the front-end and back-end of ICfabrication are enabling the continuation of the performance trends, butsuch innovations may provide only a one-time or a short-lived boost, andfundamental physical limits may soon be reached.

There are several prior art techniques that are currently employed infabricating 3D integrated circuits. In one prior art technique, thelowest device layer is fabricated on a bulk substrate or asilicon-on-insulator (SOI) substrate and then a second device layer isformed. The second device layer can be formed by epitaxial Si growth.Such a method is described, for example, in S. Pae, et al., “Multiplelayers of silicon-on-insulator island fabrication by selective epitaxialgrowth,” IEEE Elec. Dev. Lett 20:196-196 (1999). Another prior arttechnique to form the second device layer is by recrystallization of anamorphous Si layer. This approach is described, for example, in V.Subramanian, et al. “High performance Germanium seeded laterallycrystallized TFTs for vertical device integration”, IEEE Trans. ElectronDevices 45, 1934-1939 (1998); T. Kunio, et al. “Three dimensional IC'shaving four stacked active device layers”, IEDM Tech Dig 837-840 (1989);and V. W. C. Chan, et al. “Three-dimensional CMOS SOI integrated circuitusing high-temperature metal-induced lateral crystallization”, IEEETrans Elec Dev 48:1394-1399 (2001).

Subsequent processes can then be performed in such prior art techniquesto fabricate additional active devices and interconnecting wiring.Circuits fabricated in this manner suffer from two main drawbacks: (1)the recrystallized top layer often has poor electrical properties and itmay result in lower device and circuit performance; it is also difficultto control the surface orientation of the recrystallized layer; (2) thethermal cycling from the top layer formation and sequential devicefabrication degrades underlying device performance.

In some prior art techniques, 3D integrated circuits are achieved bywafer bonding. The 3D integration scheme using wafer bonding isdisclosed, for example, in R. J. Gutmann, et al. “Three dimensional (3D)ICs: A technology platform for integrated systems and opportunities fornew polmeric adhesives” Proc IEEE Int'l Conf on Polymers and Adhesivesin Microelectronics and Photonics, Germany, 173-180 (2001); R. Reif, etal. “Fabrication technologies for three dimensional integrated circuits”Proc IEEE Int'l Symposium on Quality Electronic Design 33-37 (2002); andA. W. Topol, et al. A demonstration of wafer level layer transfer ofhigh performance devices and circuits for three-dimensional integratedcircuit fabrication” Proc. AVS ICMI, 5-7 (2003).

Despite these current advances using 3D integration, there is no priorart that fabricates 3D integrated circuits having nFETs and pFETs whichare built on different surface orientations. Hence, there is a need forproviding a new and improved 3D integration scheme that allows for eachtype of device present on a semiconductor chip or wafer to be formedupon a crystallographic surface orientation that provides optimalperformance for each specific device. For example, there is a need forproviding a 3D integration scheme wherein all nFETs are built on a (100)crystallographic surface and all pFETs are built on a (110)crystallographic surface.

SUMMARY OF THE INVENTION

The present invention provides a three-dimensional (3D) integrationscheme of fabricating a 3D integrated circuit in which the pFETs arelocated on a (110) crystallographic surface and the nFETs are located ona (100) crystallographic surface. The term “3D integrated circuit” canbe defined as an IC that contains multiple layers of active devices withvertical interconnections between the layers. In a 3D IC, eachtransistor can access a greater number of nearest neighbors than in aconventional two-dimensional (2D) circuit, such that each transistor orfunctional block will have a higher bandwidth.

One advantage of 3D integration is increased packing density; by addinga third dimension to the conventional 2D layout, the transistor packingdensity can be improved thereby allowing a reduced chip footprint. Thisis particularly appealing for wireless or portable electronics. Anotheradvantage of 3D integration is that the total interconnect lengths areshorten. This provides shorter interconnect delays, less noise andimproved electro-migration reliability. A further benefit of 3Dintegration is that the overall chip performance at a given powerconsumption can be substantially improved over a conventional 2D IC.

In accordance with a first 3D integration scheme of the presentinvention, first semiconductor devices are pre-built on a semiconductorsurface of a first silicon-on-insulator (SOI) substrate that is optimalfor the first semiconductor devices and second semiconductor devices,which are different from the first semiconductor devices, are pre-builton a semiconductor surface of a second SOI substrate that is optimal forthe second semiconductor devices. After pre-building those twostructures, the structures are bonded together and interconnectedthrough wafer-via through vias.

In broad terms, the first 3D integration scheme of the present inventioncomprises the steps of:

providing a first interconnect structure comprising at least a firstsemiconductor device located on a surface of a first Si-containing layerof a first silicon-on-insulator substrate, said first Si-containinglayer having a first surface orientation that is optimal for said firstsemiconductor device;

attaching a handling wafer to a surface of the first interconnectstructure;

providing a second interconnect structure comprising at least a secondsemiconductor device that differs from the first semiconductor device ona surface of a second Si-containing layer of a secondsilicon-on-insulator substrate, said second Si-containing layer having asecond surface orientation that is optimal for said second semiconductordevice;

bonding the first and second interconnect structures to each other; and

removing the handling wafer.

In some embodiments of the present 3D integration scheme, verticalinterconnects are provided between the first and second semiconductordevices.

In addition to the first 3D integration scheme mentioned above, thepresent invention also provides a second 3D integration scheme. Thesecond 3D integration scheme of the present invention comprises:

bonding a blanket silicon-on-insulator (SOI) substrate having a firstSOI layer of a first crystallographic orientation to a surface of apre-fabricating wafer having at least one second semiconductor device ona second SOI layer that has a different crystallographic orientationthan the first SOI layer; and

forming at least one first semiconductor device in said first SOI layer.

In accordance with the present invention, the first semiconductor devicemay be a pFET and the first crystallographic orientation may be (110),while the second semiconductor device may be an nFET and the secondcrystallographic orientation may be (100). It is also possible in thepresent invention, that the first semiconductor device is an nFET andthe first crystallographic orientation may be (100) and that the secondsemiconductor device is a pFET and the second crystallographicorientation may be (110).

The present invention also provides a three dimensional (3D) integratedcircuit that includes:

a first interconnect structure comprising at least a first semiconductordevice located on a surface of a first Si-containing layer of a firstsilicon-on-insulator substrate, said first Si-containing layer having afirst surface orientation that is optimal for said first semiconductordevice;

a second interconnect structure comprising at least a secondsemiconductor device that differs from the first semiconductor devicelocated on a surface of a second Si-containing layer of a secondsilicon-on-insulator substrate, said second Si-containing layer having asecond surface orientation that is optimal for said second semiconductordevice; and

vertical interconnects connecting the first interconnect structure tothe second interconnect structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C are pictorial representations (through cross sectionalviews) illustrating a 3D integration scheme of the present invention.

FIGS. 2A-2C are pictorial representations (through cross sectionalviews) illustrating an alternative 3D integration scheme of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention, which provides 3D integration schemes for forminga 3D CMOS integrated circuit having device layers built on differentcrystal oriented SOI wafers, will now be described in greater detail byreferring to the drawings that accompany the present invention. In theaccompanying drawings, like and/or corresponding elements are referredto by like reference numerals.

In the present invention, the terms “silicon-on-insulator” or “SOI”wafer (the term ‘substrate’ can interchangeable used with the term‘wafer’) are used to define a semiconductor structure in which a buriedinsulating layer, such as a buried oxide layer, separates a topSi-containing layer (also referred to as the SOI layer or the devicelayer) from a bottom Si-containing substrate layer. The term“Si-containing” is used in the present invention to denote asemiconductor material that includes silicon. Illustrative examples ofsuch Si-containing materials include, but are not limited to: Si, SiGe,SiC, SiGeC, Si/Si, Si/SiGe, Si/SiC and Si/SiGeC. The buried insulatinglayer may be continuous or it may be non-continuous, i.e., a patternedburied insulating region. The non-continuous buried insulating regionsare discrete and isolated regions or islands that are surrounded on allsides by a Si-containing material.

The SOI substrates that are employed in the present invention are madeusing techniques well known to those skilled in the art. For example,the SOI substrates can be made by wafer bonding and cutting.Alternatively, the SOI substrates can be made by a process known asSIMOX (separation by ion implantation of oxygen). In a typical SIMOXprocess, oxygen ions are implanted into a surface of a Si-containingsubstrate and then the substrate containing the implanted oxygen ions isannealed such that a buried oxide layer forms. In yet a further method,the SOI substrate can be made by forming an insulating film atop aSi-containing substrate by deposition or thermal means, optionallypatterning the insulating layer; and then forming a top Si-containinglayer overlying the insulating film.

Notwithstanding which technique is employed, the buried insulating layerof each SOI substrate employed in the present invention typically has athickness from about 10 to about 1000 nm, with a thickness of about 100to about 200 nm being more typical. The thickness of the topSi-containing layer of each SOI substrate employed in the presentinvention is typically from about 20 to about 200 nm, with a thicknessfrom about 50 to about 100 nm being more typical. The thickness of thebottom Si-containing substrate layer of each SOI substrate employed inthe present invention is inconsequential to the present invention.

The SOI layers of each SOI substrate may have various crystallographicsurface orientations. For example, the SOI substrates may have a SOIlayer that comprises a (100) crystal orientation, or a (110) crystalorientation. In accordance with the present invention, each SOIsubstrate employed contains an SOI layer that has a different crystalorientation. Thus, the present invention contemplates the use of a firstSOI substrate having a first SOI layer of a first crystallographicorientation and a second SOI substrate having a second SOI layer of asecond crystallographic orientation, wherein the first crystallographicorientation is different from the second crystallographic orientation.

In accordance with the present invention, each SOI layer will contain atleast one semiconductor device such as an nFET or pFET, with the provisothat the at least one semiconductor device is located on acrystallographic surface that provides optimal device performance. Thus,for example, if the at least one semiconductor device, is a pFET, thepFET would be located atop a (110) crystal oriented SOI layer. When theat least one semiconductor device is an nFET, the nFET is located atop a(100) crystal oriented SOI layer.

The at least one semiconductor device is fabricated using conventionalCMOS processing steps well known to those skilled in the art. Forexample, the FETs are formed by providing a gate dielectric layer on asurface of an SOI layer, forming a patterned gate conductor atop thegate dielectric, said patterned gate conductor including an optionalpatterned hardmask located thereon, implanting dopants into the SOIlayer and optionally the gate conductor and forming sidewall spacers onvertical sidewalls of the patterned gate conductor. Trench isolationregions may be formed in each SOI substrate which extend partially, orentirely through the SOI layer stopping on a surface of the buriedinsulating layer.

After completion of the FETs, at least one interconnect level includingan interconnect dielectric having conductive lines and vias is formed onthe SOI structure utilizing a conventional back-end-of-the-line (BEOL)processing scheme. The BEOL processing includes deposition of thedielectric, patterning the deposited dielectric by lithography andetching and filling the patterned regions with a metal conductor. Asingle damascene or dual damascene technique, both of which are wellknown to those skilled in the art, may be used.

The above discussion provides some basics of the present inventionincluding terminology, materials and processes for making initialinterconnect structures that can be employed in the present invention.The following description with reference to specific drawings providesdetails of the 3D integrations schemes that may be employed in thepresent invention.

Reference is first made to FIGS. 1A-1C which illustrate a first 3Dintegration scheme of the present invention. In accordance with thefirst 3D integration scheme of the present invention, firstsemiconductor devices are pre-built on a semiconductor surface of afirst silicon-on-insulator (SOI) substrate that is optimal for the firstsemiconductor devices and second semiconductor devices, which aredifferent from the first semiconductor devices, are pre-built on asemiconductor surface of a second SOI substrate that is optimal for thesecond semiconductor devices. After pre-building those two structures,the structures are bonded together and interconnected through wafer-viathrough vias.

FIG. 1A shows an initial step of the first 3D integration scheme of thepresent invention in which a handling wafer 80 is attached to a firstinterconnect structure 10. The first interconnect structure 10 includesat least a first semiconductor device 20 located on a surface of a firstSi-containing layer 18 of a first silicon on-insulator (SOI) substrate12. In accordance with the present invention, the first Si-containinglayer 18 has a first surface orientation that is optimal for the firstsemiconductor device 20.

In one embodiment, the first semiconductor device 20 is an nFET and thefirst Si-containing layer 18 has a (100) crystal orientation. In anotherembodiment, the first semiconductor device 20 is a pFET and the firstSi-containing layer 18 has a (110) crystal orientation. The firstsemiconductor device 20 is fabricated as described above.

The first interconnect structure 10 also includes at least onedielectric 22 that has conductive wiring, i.e., lines and vias, locatedtherein. The conductive wiring is designed by reference numeral 24 inFIG. 1A.

The handling wafer 80 comprises a bulk semiconductor substrate, anotherSOI substrate or glass which is attached to a surface of the firstinterconnect structure 10 via a polymeric adhesive. In FIG. 1A, theinitial structure includes polymeric adhesive layer 28 between the firstinterconnect structure 10 and the handling wafer 80.

Illustrative types of polymeric adhesives that can be employed in thepresent invention may be conductive or non-conductive materials. Apreferred polymeric adhesive employed in the present invention is anon-conductive material. The polymeric adhesive is typically applied tothe uppermost surface of the first interconnect structure 10 andattachment is achieved by bringing the handling wafer 80 into intimatecontact with the first interconnect structure 10. The attachment may befacilitated by applying an external force to the two structures or byheating the structures to a temperature that is slightly above themelting point of the polymeric adhesive. In FIG. 1A, the arrow labeledas 30 indicates the direction in which contact occurs.

After attachment, the bottom Si-containing substrate designated byreference numeral 14 of the first SOI substrate 12 is removed by aplanarization process such as, for example, chemical mechanicalpolishing (CMP), grinding and/or etching. The planarization processstops once a surface of the buried insulating layer, designated byreference numeral 16 is reached. The arrows labeled as 32 show thisthinning step of the present invention.

A second interconnect structure 50 comprising at least a secondsemiconductor device 60 located on a surface of a second Si-containinglayer 58 of a second silicon on-insulator substrate 52 is provided andbrought into contact with the structure shown in FIG. 1A. FIG. 1Billustrates this step of the present invention. In accordance with thepresent invention, the second Si-containing layer 58 has a secondsurface orientation that is optimal for the second semiconductor device.The second pre-fabricated SOI substrate 52 also includes a bottomSi-containing layer 54 and a buried insulating layer 56. The secondinterconnect structure also includes interconnect dielectric 62 andwiring regions 64.

In one embodiment, and when the first semiconductor device 20 is annFET, the second semiconductor device 60 is a pFET that is located onthe second Si-containing layer 58 which has a (110) crystal orientation.In another embodiment, and when the first semiconductor device 20 is apFET, the second semiconductor device 60 is an nFET that is located onthe second Si-containing layer 58 that has a (100) crystal orientation.It should be noted that the first semiconductor device 20 is differentfrom the second semiconductor device 60 and that the crystallographicorientation of the first Si-containing layer 18 is different from thecrystallographic orientation of the second Si-containing layer 58.

The first and second interconnect structure (10 and 50, respectively)are then bonded to each other. Specifically, bonding of the twointerconnect structure is achieved by first bringing the two structuresinto intimate contact with other; optionally applying an external forceto the contacted wafers; and then heating the two contacted structuresunder conditions that are capable of bonding the two structurestogether. The heating step may be performed in the presence or absenceof an external force. The arrow designated by reference numeral 70denotes the direction of the contacting.

The heating step is typically performed in an inert ambient at atemperature of from about 200° to about 1050° C. for a time period offrom about 2 to about 20 hours. More preferably, the bonding isperformed at a temperature of from about 200° to about 400° C. for atime period of from about 2 to about 20 hours. The term “inert ambient”is used in the present invention to denote an atmosphere in which aninert gas, such as He, Ar, N₂, Xe, Kr or a mixture thereof, is employed.A preferred ambient used during the bonding process is N₂.

FIG. 1C shows the structure after the handling wafer 80 and the adhesivelayer 28 are removed from the bonded structures. The handling wafer 80and the adhesive layer 28 may be removed utilizing one of theplanarization process mentioned above. That is, grinding, chemicalmechanical polishing and/or etching may be used to remove the handlingwafer and the adhesive layer from the bonded structures. Alternatively,the handling wafer 80 is removed by laser ablation, and the adhesivelayer 28 is removed by a chemical etching process. FIG. 1C also showsthe presence of optional vertical interconnects 75 that are formed bylithography, etching and deposition of a conductive metal. Despite beingoptional, the vertical interconnects 75 are preferred in someembodiments of the present invention wherein a direct connection betweenthe two semiconductor devices is required.

The 3D integrated circuit shown in FIG. 1C includes semiconductordevices 20 and 60 such as nFETs and pFETs that are built upon a SOIlayer (18 or 58) of a specific crystallographic orientation that isoptimized for each device. In a preferred embodiment, the 3D integratedcircuit includes nFETs on a (100) SOI layer and pFETs on a (110) SOIlayer.

In addition to the first 3D integration scheme described above, thepresent invention also contemplates a second 3D integration scheme. Thesecond 3D integration scheme will now be described in greater detail byreferring to FIGS. 2A-2C. In the second integration scheme, a blanketSOI wafer 90 is stacked on a pre-fabricated device wafer 120 each waferhaving an SOI layer with a different crystallographic orientation. Thetwo wafers are then bonded and the blanket SOI wafer is subjected tofurther fabrication processes to make active devices and interconnects.

FIG. 2A illustrates an initial structure including a pre-fabricatingwafer 120 having second semiconductor devices 130 on a second SOI layer128. Layer 124 represents a bottom Si-containing layer and layer 126represents a buried insulating layer. The pre-fabricating wafer 120 mayalso include an interconnect region including dielectric 132 andconductive wiring 134 located therein.

Next, a blanket SOI wafer 90 having a first SOI layer 96 that has adifferent crystrallographic orientation than that of the second SOIlayer 128 is stacked atop the structure shown in FIG. 2A such that thebottom Si-containing layer 92 of the blanket SOI wafer 90 becomes theupper most layer of the stacked structure. The stacked structures arethen bonded as described above providing the structure shown in FIG. 2B.Reference numeral 94 denotes the buried insulating layer of the blanketSOI wafer 90.

The bottom Si-containing layer 92 and the buried insulating layer 94 ofthe blanket SOI wafer 90 are then removed utilizing grinding, chemicalmechanical polishing and/or etching to expose the first SOI layer 96 ofthe blanket SOI wafer 90.

First semiconductor devices 118 such as nFET or pFET are then fabricatEDon the first SOI layer 96 utilizing the techniques described above.Back-end-of the-line processing can be used to form an interconnectstructure 150 atop the now fabricated blanket SOI wafer and theabove-mentioned processing can be employed in forming the verticalinterconnects 75. The resulting structure is shown in FIG. 2C.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1-19. (Cancelled) 20 A three dimensional (3D) integrated circuitcomprising: a first interconnect structure comprising at least a firstsemiconductor device located on a surface of a first Si-containing layerof a first silicon-on-insulator substrate, said first Si-containinglayer having a first surface orientation that is optimal for said firstsemiconductor device; a second interconnect structure comprising atleast a second semiconductor device that differs from the firstsemiconductor device located on a surface of a second Si-containinglayer of a second silicon-on-insulator substrate, said secondSi-containing layer having a second surface orientation that is optimalfor said second semiconductor device; and vertical interconnectsconnecting the first interconnect structure to the second interconnectstructure. 21 The 3D integrated circuit of claim 20 wherein the firstsemiconductor device is a pFET, the first Si-containing layer has a(110) crystallographic orientation, the second semiconductor device isan nFET, and the second Si-containing layer has a (100) crystallographicorientation. 22 The 3D integrated circuit of claim 20 wherein the firstsemiconductor device is an nFET, the first Si-containing layer has a(100) crystallographic orientation, the second semiconductor device is apFET, and the second Si-containing layer has a (110) crystallographicorientation. 23 The 3D integrated circuit of claim 20 wherein said firstand second interconnect structure comprise at least a patternedinterconnect dielectric having conductive wiring located therein. 24 The3D integrated circuit of claim 20 wherein said first and secondSi-containing layers comprise Si, SiGe, SiC, SiGeC, Si/Si, Si/SiGe,Si/SiGeC or any other semiconductor material that includes silicon. 25The 3D integrated circuit of claim 20 wherein said first and secondsilicon-on-insulators each comprise a buried insulating layer beneathsaid Si-containing layers. 26 The 3D integrated circuit of claim 25wherein said buried insulating layer is continuous. 27 The 3D integratedcircuit of claim 25 wherein said buried insulating layer isnon-continuous. 28 The 3D integrated circuit of claim 25 wherein saidburied insulating layer has a thickness from about 10 to about 1000 nm.29 The 3D integrated circuit of claim 28 wherein said thickness is fromabout 100 to about 200 nm. 30 The 3D integrated circuit of claim 20wherein said first and second Si-containing layers each have a thicknessfrom about 20 to about 200 nm. 31 The 3D integrated circuit of claim 30wherein said thickness is from about 50 to about 100 nm. 32 The 3Dintegrated circuit of claim 20 wherein said first semiconductor deviceand said second semiconductor device are both field effect transistors.33 The 3D integrated circuit of claim 20 wherein said first interconnectstructure and said second interconnect structure are joined togetherwith a polymeric adhesive.